1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In particular, the present invention relates to a semiconductor device that includes a thin gate insulating film and a method for manufacturing the semiconductor device.
2. Description of the Related Art
In LSIs (large scale integrated circuits), miniaturization of the elements, i.e., MOSFETs (metal oxide semiconductor field effect transistors) and a decrease in operating voltage have been pursued to increase the degree of integration per chip. With the achievement of highly integrated elements, a polymetal gate that uses a tungsten film instead of a tungsten silicide film for word lines has been studied to improve the speed of the elements. The specific resistance of the tungsten film is even lower than that of the tungsten silicide film.
For example, JP 11(1999)-261059 A discloses a method for fabricating a single p-channel MOS (metal oxide semiconductor) transistor that includes a polymetal gate with a conventional LP-SiN (low pressure chemical vapor deposition silicon nitride) film by using a STI (shallow trench isolation) process. FIGS. 9A to 9D are cross-sectional views showing the method in order. First, shallow trenches for isolation (STI) 161 are formed in a substrate 141, and then an n well 151 is formed by ion implantation of phosphorus (P) and arsenic (As) into a region between the trenches (FIG. 9A).
A RTP (rapid thermal process) is performed to form a gate insulating film 11 of an oxide film or oxynitride film. Using a LPCVD (low pressure chemical vapor deposition) chamber, an amorphous Si film 12 is grown in a SiH4 atmosphere, and then is doped with boron (B) by ion implantation. A titanium nitride (TiN) film 14 and a tungsten (W) film 15 are deposited in the order mentioned. A LP-SiN film 16 that serves as a gate-cap layer is formed on the tungsten film 15 in an atmosphere of SiH2Cl2 (dichlorosilane, which may be abbreviated as “DCS” in the following) and NH3. On top of that, a photoresist pattern 17 is formed to provide a gate pattern (FIG. 9B). The boron-implanted amorphous Si film 12, the titanium nitride film 14, and the tungsten film 15 constitute a gate electrode 18 in the subsequent process.
By using the photoresist pattern 17 as a mask, etching is performed to form a polymetal gate (gate electrode) 18 (FIG. 9C).
A side wall 19 is formed with the LP-SiN film. The side wall 19 is used to provide a LDD (lightly doped drain), a source (p+) 171, a drain (p+) 172, etc. (FIG. 9D).
For the polymetal gate thus produced, however, a large amount of hydrogen (H) is included in a range from the surface of the gate cap layer 16 to a depth of about 125 nm (FIG. 10). In FIG. 10, the horizontal axis indicates a depth (nm) from the surface of the LP-SiN film 16 (the gate cap layer) shown in FIG. 9D, and the vertical axis indicates the hydrogen concentration (atoms/cm3). The LP-SiN film 16 is formed of a SiH2Cl2 gas including a Si—H bond and a NH3 gas including a N—H bond. Therefore, unreacted Si—H and N—H bonds remain in the silicon nitride film, so that a large amount of hydrogen (H) is entrapped. The unreacted Si—H and N—H bonds are separated by various heat treatments after the deposition of LP-SiN to generate hydrogen. This hydrogen diffuses into the gate insulating film and acts as an electron trap, causing a shift in the threshold voltage (Vth) of a MOSFET and the degradation of an on-state current (Ion).